Various types of flat panel displays such as liquid crystal displays (LCDs), plasma display panels (PDPs), electroluminescence display panels, LED display panels, etc., have been developed to replace traditional cathode ray tube (CRT) displays. Such flat panel displays are suitable for devices and applications requiring small dimension, light weight and low power consumption. For example, LCDs can be operated using a large scale integration (LSI) driver since LCDs can be driven by a low-voltage power supply and have low power consumption. Accordingly, LCDs have been widely implemented for laptop computers, pocket computers, automobiles, and color televisions, etc. The light weight, smaller dimension, and lower power consumption features of LCD devices render such display devices suitable for use with, e.g., portable, handheld devices.
In general, the signals that are used for driving flat panel displays are voltage or current signals that are either proportional or inversely proportional to the desired brightness of pixels of the display. The driving signals are generated from driving devices/apparatus (which include semiconductor integrated circuits (ICs)) disposed adjacent to the display panel. Depending on the display type, the driving signals will operate to change the panel electrically or optically.
FIG. 1 is a schematic diagram that illustrates a conventional display system. The display system (100) comprises a display panel (110) (e.g., LCD) and a plurality of components for driving/controlling the display panel (110) including, e.g., a controller (120), a gate driver IC (130) and a source driver IC (140). The display panel (110) comprises a plurality of data lines (DL1˜DLn) that are connected to the source driver IC (140) and a plurality of gate lines (GL1˜GLn) that are connected to the gate driver IC (130). The display panel (110) comprises a plurality of pixels arrayed in a matrix of rows and columns, wherein the pixels in a given row are commonly connected to a gate line (GLi) and wherein the pixels in a given column are commonly connected to a data line (DLi). The display panel (110) displays an image in response to source signals output to the data lines (DL1˜DLn) from the source driver IC (140) and gate driver control signals output to the gate lines (GL1˜GLn) from the gate driver IC (130).
More specifically, the controller (120) receives as input a plurality of driving data signals and driving control signals that are output from an image supply source (e.g., a main board of a computer). The driving data signals comprise R, G, B data for forming an image on the display (110). The driving control signals comprise vertical synchronous signals (Vsynch), horizontal synchronous signals (Hsync), a data enable signal (DE) and a clock signal (Clk). The controller (120) outputs to the source driver IC (140) a plurality of data signals R′, G′ and B′ (driving data), which correspond to the input R, G, B data, and a source control signal (SC) (driving control signal). The controller (120) outputs a gate control signal (SG) to control the gate driver IC (130).
The gate driver IC (130) receives as input a plurality of DC voltages including VDD (logic power supply voltage), VSS (logic ground voltage), VGH (gate driver turn-on voltage), VGOFF (gate driver turn-off voltage) and VCOM (common electrode voltage). The gate driver IC (130) outputs gate driver controls signals (having logic levels of VGH or VGOFF) to the gate lines (GL1˜GLn) to drive selected gate lines. The source driver IC (140) determines source signals to be output to the data lines (DL1˜DLn) in response to the data signals (R′, G′, B′) and the source control signal (SC).
The controller (120) controls the timing for which data and control signals are output from the source driver IC (140) and gate driver IC (130). For example, in one mode of operation, the controller (120) generates the control signals SC and SG such that the gate driver IC (130) transmits a gate driver output signal VGH to each gate line (GL1˜GLn) in a consecutive manner and data voltage is selectively applied to each pixel in an activated row one by one in order. In another mode of operation, the pixels can be charged by sequentially scanning pixels in a first column and thereafter scanning pixels in a next column.
Assuming the display panel (110) is a TFT-LCD, the display panel (110) would include a thin-film transistor (TFT) board comprising a plurality of pixel units arranged in matrix form. As shown in FIG. 1, each pixel unit comprises a TFT (150), a liquid crystal capacitor (151), which is connected between a drain electrode of the TFT (150) and a common electrode (VCOM), and a thin-film storage capacitor (152), which is connected in parallel with the liquid crystal capacitor (151). The storage capacitor (152) stores an electric charge so that an image on the display is maintained during a non-selected period. The liquid crystal capacitor (151) is formed by a common electrode (VCOM) of a color filter plate, a pixel electrode of the TFT (150) and liquid crystal material therebetween. A source electrode of the TFT (150) is connected to a data line (DL1) and a gate electrode of the TFT (150) is connected to a gate line (GL1). The TFT (150) acts as a switch that applies a source voltage on the data line (DL1) to the pixel electrode when a gate driver signal of VGH on the gate line (GL1) is applied to the gate of the TFT (150).
FIG. 2 is a block diagram that schematically illustrates a gate driver IC having a conventional architecture, which can be implemented in the system of FIG. 1 for driving a flat panel display such as a TFT-LCD. In general, as depicted in FIG. 2, a conventional gate driver (200) comprises a row driver selecting unit (210), a line decoder (220), voltage level shifter circuits (230) and buffers (drivers) (240). The row driver selecting unit (210) generates a gate line control signal, G[m:0] in response to a driver control signal (STV) that specifies one of a plurality of gate lines (GL1˜GLn) to be selected. The line decoder (220) comprises a plurality of line decoders (220-1˜220-n), each associated with one of the gate lines (GL1˜GLn). Each line decoder (220-1˜220-n) decodes the gate line control signal G[m:0] and generates a corresponding decoded gate line control signal (GD[1]˜GD[n]).
The voltage level shifter circuits (230) comprise a plurality of separate level shifter circuits (230-1˜230-n), each associated with one of the gate lines (GL1˜GLn). Each level shifter circuit (230-1˜230-n) receives a corresponding decoded gate line control signal (GD[1]˜GD[n]) output from a corresponding line decoder (220-1˜220-n). DC voltages, VGH and VGOFF are applied to each level shifter circuit (230-1˜230-n), wherein VGH is a predetermined gate driver turn-on voltage (e.g., +15 v) and VGOFF is a predetermined gate driver turn-off voltage (e.g., −8 v). Each level shifter (230-1˜230-n) changes the voltage level of a corresponding decoded gate line control signal (GD[1]˜GD[n]) from VDD to VGH or from VSS to VGOFF. The buffers (240) comprise a plurality of buffers (drivers) (240-1˜240-n)) that are connected to the output of corresponding level shifters (230-1˜230-n), for driving corresponding gate lines (GL1˜GLn) via corresponding gate driver output signals (G1˜Gn). Details regarding operation of a level shifter circuit and buffer are described below with reference to FIG. 3.
FIG. 3 is a circuit diagram illustrating a conventional level shifter circuit and output buffer, which can be implemented in the gate driver circuit of FIG. 2. For purposes of illustration, FIG. 3 depicts circuit architectures of a voltage level shifter (230-i) and corresponding buffer (driver) (240-i), which can be implemented for each of the level shifters (230-1˜230-n) and buffers (240-1˜240-n) shown in FIG. 2. The level shifter (230-i) comprises a plurality of NMOS transistors (NT1˜NT6) and a plurality of PMOS transistors (PT1-PT6) operatively connected as shown. The level shifter (230-i) receives as input the decoded gate line control signal GD[i] output from a corresponding line decoder (220-i). In the illustrative embodiment, the decoded gate line control signal GD[i] comprises GD[i] (which is VDD or VSS) and its complement GDB[i]. The level shifter (230-i) also receives as input DC voltages VGH and VGOFF. The buffer (240-i) comprises two inverters, a first inverter comprising PMOS transistor (PT7) and NMOS transistor (NT7), and a second inverter comprising PMOS transistor (PT8) and NMOS transistor (NT8).
FIG. 4 is a waveform diagram illustrating operation of the circuit of FIG. 3. More specifically, FIG. 4 illustrates the gate driver voltage (Gi) that is output to gate line (GLi) based on the logic level of the decoded gate line control signal (GD[i]/GDB[i]). As shown in FIG. 4, when the logic level of GD[i]=VDD and the logic level of GDB[i]=VSS, the gate line voltage GLi=VGH (e.g., +15 v) to activate (turn-on) the gate line. When the logic level of GD[i]=VSS and the logic level of GDB[i]=VDD, the gate line voltage GLi=VGOFF (e.g., −8 v) to deactivate (turn-off) the gate line.
Although the operation of the level shifter and buffer circuit of FIG. 3 is known and readily understood by those of ordinary skill in the art, a brief description will be provided. Assume GD[i]=VDD and GDB[i]=VSS. A logic “1” is applied to the gate of NT1 and a logic “0” is applied to the gate of NT2. As such, NT1 is turned on and NT2 is turned off, causing node N1 to be pulled down to logic “0” and node N2 is floating. With node N1 at logic “0”, PMOS transistors PT2, PT3 and PT5 will be turned on, which causes VGH to be applied to the gates of transistors NT3 and NT6 to turn on such transistors.
When designing display panel systems (such as shown in FIG. 1), it is highly desirable to provide architectures that reduce the size of such systems, especially when such systems are implemented for small, handheld portable devices (e.g., PDAs, etc.). One way in which the size of such display systems can be reduced is by reducing the size of the IC chips that are used to drive the display panel. The architecture of the conventional gate driver circuit as described above (FIGS. 2 and 3) is disadvantageous in this regard because the level-shifter circuits (230) occupy a significant amount of space, which results in an increase of the chip size of the gate driver IC. Indeed, as shown in FIG. 2, the conventional gate driver circuit comprises n voltage level shifters (230-1˜230-n), and as shown in FIG. 3, each voltage level shifter (230-1˜230-n) comprises 12 high-voltage transistors—six (6) PMOS and six (6) NMOS transistors, each of which are constructed to be significantly large due to the wide voltage range (e.g., VGH=+15 v and VGOFF=−8 v). As the range of level shifting becomes wider, the size of such transistors must be increased for proper operation. In the conventional architecture described above, the level shifter circuits (230-1˜230-n) occupy approximately 50% of the total chip size of the gate driver IC.